How To Divide A Register

One bug yous hit equally you lot tackle complex projects in your electronics hobby is the need to run things at different speeds.

As fourth dimension is the essence of digital logic you'll start to want to explore irresolute the length of said time periods. Inn fact, logic itself relies on having discrete periods of time in which to switch $.25 between 1s and 0s.

Clock management is a perfect skill for folks coming from an Arduino background to main: so let'southward become to it. We're going to prove how to divide frequencies using digital logic.

What did yous build that required multiple clicks?

In another post, I discussed how I multiplied a clock using only digital logic. I desire to impress something on you: don't practise that for a product piece of hardware. A real solution requires feedback! (Check out our PLL multiplication post here).

Digital Clock Segmentation Theory: Phase Relationships, and Perfect and Anticipated Divided Clocks

While determining the requirements for my contempo project, I determined I needed a few clocks.

Folks who have worked with video in the past will probably recognize a few of them - and note that I decided to 'round' things off a lilliputian:

Base: 3.5795454 MHz ( (5*7*9)/(8*xi) MHz)
Pixel: 12.528 MHz (7/ii * Base of operations)
Other: 25.0568 MHz (7 * Base of operations)

Don't get hung up on the exact numbers. This particular project was a video projection, but as long as y'all make up one's mind up forepart what clocks you need and how much you can 'cheat' you can reach similar things.

We'll hash out a bit of the theory, just concentrate more on the practical applications.

Here'due south the thing: sectionalization of a clock is elementary compared to multiplication. If you have a nice, 50% duty clock coming into your projection, you lot can hands make other 50% clocks at a slower speed. It's peculiarly unproblematic to divide clocks if you have an even integer divisor.

For our project, we started with a 14.31818 MHz oscillator - .49 cents on eBay, and 4x our Base Clock.

(Nosotros adopt total tin designs. Y'all tin use a crystal with two leads, but getting these things to oscillate properly on your own is harder.)

Methods of Clock Partitioning

Dividing Clocks with the Simple Flip Flop Method

Most sites recommend using normal flip-flops to carve up a clock.

Yous can Google effectually for more than detail, but in our schematic we utilize a D-Flip-Flop to toggle dorsum and forth between a one and a 0 by feeding back the opposite of the data to the input. This finer divides our clock past 2:

There are ii 'events' every clock bike - a low to high movement, and a loftier to low movement. The flip-flops will toggle on every positive - depression to high - border, so you effectively only get 1 'consequence' per clock. Bam, unproblematic division past ii, combine a few in fun ways to easily carve up by powers of two while matching the clock's duty cycle.

Note, besides, that you can create very circuitous methods to divide clocks by non-powers of ii. Using and and or gates, you can effectively cord together flip flop outputs to lucifer your fifty% duty cycle.

Here's a proficient paper with some examples, from a Xilinx engineer.

Note that for this project, we carve up our clock past 4, then 2 (so... 8). We then multiply by fourteen to get around dividing past four and multiplying by 7. The odd integer created too much chip inflation for our gustatory modality.

Dividing Clocks with The Shift Register Method

1 part most everyone who has played around with an Arduino has in their parts drawer? The venerable 74**595.

Now, this role is usually used as a "port expander" on an Arduino. Using ane pivot, you can control as many pins equally you need at a slower speed than your system clock.

Hither'southward something else that'southward pretty cool: what yous put into the input comes out of the output at a known rate. By introducing feedback yous can carve up your original clock.

Using this method you can separate a clock by 2, 4, 6, 8, 10, 12, 14, or sixteen by only calculation an inverter! Chain a few together and you've got most whatsoever clock you demand.

(As an added bonus for our project, you can sample whatever of the outputs to get your desired clock. All of Q0-Q7 in our schematic are running at 3.5795454 MHz, a huge bonus for a video project.

We get 4 phases here - "0 degrees" and xc, 180, and 270. If y'all started with a 28.6363 MHz clock? You'd brand all 8 outputs useful by getting 8 phases!)

Digital Clock Division Do: Build Our Clock Divisor in the Lab!

I've omitted some parts in this schematic, namely attempting to necktie off unused inputs (especially on CMOS parts, see datasheets) and decoupling capacitors on some of the pins. If y'all follow this projection, note that 25 MHz on a breadboard is starting to push button the extremes of reliability - so practice all you lot can for reliable performance.

Parts Listing:

14.31818 MHz Oscillator (effort eBay)
74HC595 Shift Register
74F74N D-Blazon Flip Flops (eBay...)
74F14N Schmitt Trigger Inverters (Ditto)

Note: The 74HC595 would exist ameliorate replaced by a shift register without a latch enable.

As well notation we don't specially care if the clock starts low or high when we ability on. Nosotros invert the output, which will exist a '?' at startup. If y'all use this concept in a hardware pattern language, initialize it to either high or low.

Shift Register and a Flip-Flop to Divide Frequencies — Shift Register and Flip-Flop to Split Frequencies (Click to Zoom)

Digital Clock Partition Bonus! Split up Frequencies in Hardware Design Languages

Our eventual terminate point for that 25.xxx MHz clock was a CPLD, a "Complex Programmable Logic Device".

In the abstruse, a CPLD is a cousin to the Field Programmable Gate Array (FPGA). Information technology has some benefits like instant configuration on power-upwards and lower power usage and footprint. Notwithstanding, CPLDs more often than not lack the huge number of resource nowadays day FPGAs offer.They can be programmed with a Hardware Pattern Language, just like an FPGA.

Hither's an case of dividing a 25.0568 MHz clock by 7 in VHDL (just take 'nots' of each output for 7 more phases!).

-- Define the shift register:

signal PHASE_SHIFTER : unsigned(six downto 0) := "1111111";

... -- Skip a few lines

process(CLK)
begin

if (CLK'event) and then
PHASE_SHIFTER <= unsigned(PHASE_SHIFTER (five downto 0)) & not PHASE_SHIFTER(half-dozen);
end if;

finish process;

(Yes, I'm American. Yes, I learned Verilog first. I just savor VHDL more.)

Note: you'll demand a CPLD/FPGA family which has flip flops which can clock on both edges to use the above lawmaking ("CLK'Event"). I used a 64 macrocell Coolrunner 2 from Xilinx.

What methods take you lot used? See anything wrong with the piece as presented? Did it work for you? What projects accept y'all completed that required clock manipulation?

Post us with whatever questions or comments.